====== FPGA ======
===== Links =====
  * [[http://jjackson.eng.ua.edu/courses/ece480/lectures/|Sehr ähnlicher Kurs]]
  * [[http://www.ics.uci.edu/~jmoorkan/vhdlref/|"Kurz" Dokus]]
  * [[http://tams-www.informatik.uni-hamburg.de/research/vlsi/vhdl/index.php?content=03-documentation|VHDL Link Sammlung]]
  * [[http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm|Xilinx ISE WebPACK]]
  * [[https://wiki.archlinux.org/index.php/Xilinx_ISE_WebPACK|Installationsanleitung für Arch Linux]]


===== Board =====
  * **Hersteller**: [[http://www.digilentinc.com|Digilent]]
  * **Produkt**: [[http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,789&Prod=NEXYS2|Nexys2]]
==== Chip ====
  * Hersteller: Xilinx
  * SpartanE3 XC3E500E

^                System gates ||      500k |
^  CLBs ^              Breite |         34 |
^   ::: ^                Höhe |         46 |
^   ::: ^              Gesamt |       1164 |
^                      Slices ||      4656 |
^             Distributed RAM ||   73k Bit |
^                   Block RAM ||  360k Bit |
^                 Mulitiplyer ||        20 |
^                        DCMs ||         4 |
^               Max. user I/O ||       232 |
^  Max. differecial I/O pairs ||        92 |

===== Zusamenfassung =====
  * [[hw]]
  * [[syntax]]
  * [[circuits]]
  * [[tools]]